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Platform Designer (Standard) allows memory-mapped connections between AMBA® 3 AXI components, AMBA® 3 AXI and AMBA® 4 AXI components, and. AMBA®. AXI Protocol. Version: Specification Subject to the provisions of Clauses 2, 3 and 4, ARM hereby grants to LICENSEE a. AMBA® AXI4 (Advanced eXtensible Interface 4) is the fourth generation of the AMBA the AXI4 specification for high-performance FPGA-based systems and designs. The Xilinx AXI Reference Guide guides users through the transition to AXI4 3rd party IP and EDA vendors everywhere have embraced the open AXI4 .

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Most signals are allowed. However, the following limitations are present in Platform Designer Standard It does not change the address, burst length, or burst size of non-modifiable transactions, with the following exceptions:.

Advanced Microcontroller Bus Architecture – Wikipedia

Platform Designer Standard ignores all other bits, for example, read allocate or write allocate because the interconnect does not perform caching. It does not use or modify the PROT bits. To prevent reordering, for slaves that accept reordering depths greater than 0, Platform Designer Standard does not transfer the transaction ID from the master, but provides a constant transaction ID of 0.


For slaves that do not reorder, Specitication Designer Standard allows the transaction ID to be transferred to the slave.

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To avoid cyclic dependencies, Platform Designer Standard supports a single outstanding slave scheme for both reads and writes. Changing the targeted slave before all responses have returned stalls the master, regardless of transaction ID.

ID width limited to bits. Data widths limited sxi a maximum of bits Limited to a fixed byte width of 8-bits. Low power extensions are not supported in Platform Designer Standardversion All responses must come from the terminal slave.

Platform Designer Standard interconnect acknowledges the cacheable modifiable attribute of AXI transactions.

Exclusive accesses are supported for AXI slaves by passing the specifictaion, transaction ID, and response signals from master to slave, with the limitation that slaves that do not reorder responses.

Locked accesses are also not supported. Full response signaling is supported.

Platform Designer Standard interconnect provides responses in the same order as the commands are issued. Narrow bus transfers are supported. AXI write strobes can have any pattern that is compatible with the address and size information.


Byte 0 is always bits [7: Unaligned address commands are commands with addresses that do not conform to the data width of a slave.

Unaligned transfers are aligned if downsizing occurs. Platform Designer Standard specirication Read side effects can occur when more bytes than necessary are read from the slave, and the unwanted data that are read are later inaccessible on subsequent reads.

For write commands, the correct byteenable paths are asserted based on the size of the transactions.

For read commands, narrow-sized bursts are broken up into multiple non-bursting commands, and each command with ambx correct byteenable paths asserted. Platform Designer Standard always assumes that the byteenable is asserted based on the specifciation of the command, not the address of the command. The following scenarios are examples: For a bit AXI master that issues a read command with an unaligned address starting at address 0x01with 4-bytes to an 8-bit AXI slave, the starting address is: